The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to methods for forming interconnects that include cobalt.
An interconnect structure may be used to electrically connect device structures fabricated on a substrate by front-end-of-line (FEOL) processing. A back-end-of-line (BEOL) portion of the interconnect structure may include metallization formed using a damascene process in which via openings and trenches etching in a dielectric layer are filled with metal to create features of a metallization level. The lowest metal level of the BEOL interconnect structure may be coupled with the device structures by features, such as contacts, that are formed by middle-of-line (MOL) processing prior to BEOL processing.
Cobalt is a candidate material to replace tungsten in the metallization of the MOL portion of the interconnect structure and to replace copper in the metallization of the BEOL portion of the interconnect structure. With scaling to smaller feature sizes (e.g., 7 nm and smaller nodes), BEOL and MOL features characterized by high aspect ratios of depth to width may be difficult to fill without pinch-off and the formation of voids.
Improved methods are needed for forming interconnects that include cobalt.